Within computer instruction processing, branch prediction generally requires an access into an array of prediction information. For many prediction systems and methods, the location of the information within the array depends on recent history of branch behavior. While such an array is typically stored within a processor, e.g., a microprocessor, accessing the array is not instantaneous, e.g., such an access may take a few clock cycles. Unfortunately, such a prediction array access time increases the time required for a branch prediction to update an instruction fetch unit. For example, predicting a branch to be taken generally places a new, non-consecutive address into the fetch unit of an instruction pipeline. As an unfortunate result, such increased update time also increases the duration of an instruction pipeline stall for a “branch taken” prediction.